In the current state of technology, integrated circuits (ICs) play a major role. In almost every electronic application, there are not just one but many ICs that are utilized. To reduce manufacturing costs and increase functionalities, ICs have become smaller and more dense with incredible complexities over the years. The increase in miniaturization and complexity is often coupled with the need to have more interconnects (i.e., pads) to other ICs and/or a substrate (e.g., a circuit board). The spacing between the pads (pitch) is often governed by manufacturing and assembly limitations. The pitch governs how many pads can be provided on an IC. As a result of this limitation, in some instances a sufficient number of pads is not available (i.e., the IC is pad limited) for all the necessary interconnects.
Also, many electronic systems are implemented in a single chip package where the entire system is integrated on a common packaging substrate. In addition, wafer-level integrated passive device (IPD) technology has been developed offering high performance solutions, reducing board level complexity, and improving ease of passive assembly. Also, many efforts to improve circuit bandwidth and density have been made based on 3-dimensional integration packaging technologies. This 3-D circuitry can shorten interconnects to reduce parasitic capacitance, resistance, and inductance, resulting in higher speed and functionality, and reduce interconnect powerloss and crosstalk. These advantages are, for example, successively applied to integrating sensors and front end electronics within pixel cells in display applications for higher performance. In addition, a wafer-scale heterogeneous integration technology has been recently developed in which batch fabrication capability, high interconnect density, high integration level, and compactness with comparable system cost are combined. These developments enable going beyond the limitation of monolithic devices in a compact form factor, offering both the performance advantages (gain and bandwidth) of III-V compound devices coupled with incredible integration level of silicon material.
Integration of III-V devices on a complementary metal oxide semiconductor (CMOS) silicon substrate remains a challenge given that the state-of-the-art input and output pitch sizes are 200 μm. In addition, many three dimensional silicon-on-silicon IC arrangements also pose a challenge for interconnectivity of pads associated with each IC. In many cases, given the fast pace of integration and development of technologies, however this pitch size is incompatible with the required number of pads.
One way to address the required number of pads is to use the pads for multiple purposes, e.g., pads used for a test mode and an operational mode. However, multi-use pads lead to additional complexity both from construction as well as operation.
Another way to address the required number of pads is to reduce the pitch between the pads. There are several interconnect technologies that affect the pitch. In wirebond technology, wires are connected between the pads and external components (i.e., pads of another IC or landing traces on a circuit board). In flipchip technology, bumps formed on pads are utilized to make the required connection. Other technologies are also available, e.g., multichip bonding approaches to three-dimensional ICs utilizing through-silicon-vias (TSV) for making interconnectivity between the several ICs and the substrate. In each of these technologies, several factors are involved in determining the minimum pitch in a fine-pitch interconnection arrangement between one IC and another IC or a substrate. These fine-pitch factors include crosstalk between wires resulting from cross-capacitance, parasitic resistance and inductance, all of which affect operational speed and functionality of the affected devices.
One way to reduce the pitch is to use an isotropic conductive adhesive (ACA) between the pads and other interconnection, as known to a person of ordinary skill in the art. The ACA includes a curable resin with conductive particles dispersed therein with a uniform density. Using ferromagnetic conductive particles allow alignment of these particles as a function of an applied external magnetic field. Referring to FIG. 10, a prior art ACA arrangement 10 is depicted as an approach to interconnecting pads. The ACA arrangement 10 is defined by substrates 12 and conductive pads 14. For improved conductivity, conductive pads 14 can be made from gold, silver, copper, or other highly conductive material. The conductive pads 14 are in contact with the substrates 12, thereby electrically coupling to the substrates 12. The ACA includes a curable resin 16 in which ferromagnetic conductive particles 18 are uniformly dispersed (not shown). Application of an external magnetic field 20, causes formation of poles (N and S) on the ferromagnetic conductive particles 18. Further, upon application of the external magnetic field 20, the ferromagnetic conductive particles 18 interact with each other and align along direction of the magnetic field 20 with a non-uniform alignment dispersion 22, as depicted in FIG. 10. While not shown, there may be stray ferromagnetic conductive particles 18 dispersed throughout the curable resin 16, resulting in a heightened parasitic capacitance. Once the ferromagnetic conductive particles 18 are aligned, the curable resin 16 can be cured to lock the ferromagnetic conductive particles 18 in place.
One benefit in the prior art ACA application depicted in FIG. 10 is that it has good performance in high-density applications with input/output (I/O) pads of less than 100 μm×100 lam in area. This benefit is arrived at because the formed columns are substantially insulated from the closely-located neighboring pads. However, the ACA arrangement of the prior art may result in high resistance values because the number of vertical conductive columns (three shown) depends on the portions of the pads 14 that are overlapped. Additionally and more specifically, physical contact between the ferromagnetic conductive particles 18 and the pads 14 is weak when compared to conventional bonding techniques (TSV and solder bumps). In addition, in certain manufacturing circumstances the ferromagnetic particles forming the columns in the prior art ACA interconnects may even result in open circuits. Therefore, there is a fundamental limitation as to how low a resistance (<0.88Ω at 100 μm×100 μm pad area) can be achieved with the ACA arrangement of the prior art.
In the situation as depicted in FIG. 10, one goal is to generate well formed columns of ferromagnetic conductive particles 18 between the pads 14 in order to provide high current density capabilities with low ohmic contact resistance. Another goal is to reduce parasitic capacitance between the column that are formed between the pads 14 and the column that are formed outside the pads 14. As shown in FIG. 10, the interaction between the ferromagnetic conductive particles 18 and the pads 14 can only meet the desired goals in a limited fashion. Specifically, the current carrying capability along columns of the ferromagnetic conductive particles 18 in between the pads 14 is limited to how tightly these particles form in the columns. Small gaps between the ferromagnetic conductive particles 18 can cause the resistance between the pads to increase dramatically. The density of columns is a function of the loading density of the original particles in the epoxy, which is fundamentally limited if separate columns are to be formed since agglomeration occurs with a high loading density. This limit means that there will always be sparse columns on the pads unless a new process is developed in which columns are preferentially formed in desired locations. In addition, the non-uniform alignment dispersion 22 between the columns that are formed between the pads 14 and the columns that are formed outside the pads, can result in a high parasitic capacitance.
Furthermore, weakening of the contact junction between the ferromagnetic conductive particles 18 and between the particles 18 and the pads 14 in presence of external thermal energy is also a major challenge. This weakening occurs because of a large difference of coefficient of thermal expansion (CTE) of the epoxy material and the particles.
Therefore, a simple and low-cost interconnection technology is needed that meets fine-pitch interconnection requirements allowing devices to operate at desired speed and functionality, provide superior ohmic characteristics between interconnects and minimize parasitic capacitance.